This invention relates to digital circuits. In particular, the invention relates to pre-scaler.
Pre-scaler circuits are useful in many applications such as clock generation in digital circuits and phase-locked loop (PLL) circuits. It is usually desired to divide a clock signal by an integer N.
Existing techniques to provide divide-by-N uses a series of divide by ⅔ sections. These techniques are limited to division ratios between 2k and 2k+1xe2x88x921, where k is the number of the 2-3 cells in cascade. These techniques therefore cannot be used for division ratios beyond the bands of 2k and 2k+1xe2x88x921. In addition, the reloading of these circuits is done asynchronously by a separate strobe signal. The asynchronous reloading typically leads to additional hardware, added power consumption and high noise.